1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a semiconductor device mounted on a package substrate capable of reducing signal noises.
2. Description of the Related Art
In recent years, the operational speed of semiconductor devices has been increased on one hand, while their power consumption has been reduced on the other hand. This leads to various problems which need not be addressed according to prior arts. The problems include those relating to signal integrity (SI) and power integrity (PI). The SI relates to a transmission waveform quality during signal transmission in a semiconductor device. The SI ensures digital signals having wide frequency components are transmitted without deterioration and with the transmission waveform quality being kept high. The PI relates to high-voltage (VDD) and low-voltage (ground) power supply quality. When the power supply is not stable, it will cause insufficient power supply to a transmission circuit connected to the power supply, which will in turn cause variation in power supply voltage, disturbance in signal waveform, and radiation noises, resulting in deterioration of the signal waveform.
The signal deterioration is caused by various factors, including, inter alia, noises caused by high-speed signals. Referring to FIG. 1 description will be made of deteriorated signal waveforms and causes thereof. FIG. 1A depicts an ideal signal waveform 1. The signal waveform 1 takes a form of a rectangular wave which has a low-level portion, a rising portion, a high level portion, and a failing portion shown by straight lines. This waveform is put in ideal conditions for all factors including stability in power supply voltage.
However, as the operational speed of the semiconductor device is increased and the signal speed is increased, disturbance in actual signal waveforms becomes more notable. The signal waveform is susceptible to the noise due to ringing (multiple reflection caused by impedance mismatching possibly occurring during connection of transmission lines or components), overshoot or undershoot. As shown in FIG. 1C, the resulting waveform includes an overshoot 3 and an undershoot 4. The overshoot 3 and the undershoot 4 are generated when rising and falling portions of a signal output by a driver momentarily exceed a fixed high/low level. Accordingly, in practice, measures are taken so that the overshoot 3 and the undershoot 4 are minimized in an actual signal waveform 2 as shown in FIG. 1B.
In addition, power supplies have problems such as a simultaneous switching noise. The simultaneous switching noise will be described with reference to FIG. 2. The reference numeral 5 denotes a high-voltage power supply line (VDD), 6 denotes a low-voltage ground line (VSS), 7 denotes a current path occurring during operation, and 8 denotes a transistor. When all the transistors 8 are simultaneously switched over, a current will be fed to all the current paths 7-1 to 7-N simultaneously. This means that the current path 7 should supply the current to all of the current paths 7-1 to 7-N.
Consequently, a large current flows through the power supply line 5, which increases the electromotive force and results in noise generation. This is so-called simultaneous switching noise. Such problem has been addressed by using a multilayer substrate for enlarging the area of power supply and ground lines, or by mounting by-pass capacitors and damping resistors, or by performing impedance matching. However, the increased speed, the reduced size and the increased density of the semiconductor device have made it difficult to enlarge the area of the power supply and ground lines or to arrange a sufficient number of by-pass capacitors or damping resistors. This causes problems of disturbance in the signal waveform and deterioration of the signal quality.
Some prior art patent documents refer to deterioration of signal waveform as described below. Japanese Laid-Open Patent Publication No. 2003-283148 (Patent Document 1) describes a multilayer wiring board in which a power supply layer and a ground layer are formed by a laminate structure consisting of a low-resistance conductor layer and a high-resistance conductor layer. Both the power supply layer and the ground layer have a high-resistance conductor layer on their surfaces facing each other so that the variation in power supply voltage or the radiation noise possibly occurring in the power supply layer or the ground layer is thereby suppressed. Japanese Laid-Open Patent Publication No. 2003-234429 (Patent Document 2) describes a chip size package (CSP) having a semiconductor chip mounted thereon, in which a coating layer of a high-resistance metal material is provided on one surface of a wiring pattern for connection between the semiconductor chip and a bump electrode.
Japanese Laid-Open Patent Publication No. 2003-332735 (Patent Document 3) describes a technique in which there are provided patterns having a high resistivity and isolated from each other (referred to as anchor portions) on a part of the wiring pattern surface in contact with an insulating layer of a wiring board. Japanese Laid-Open Patent Publication No. 2004-087928 (Patent Document 4) describes a technique in which the mutually facing surfaces of wiring conductor layers transmitting high-frequency signals are formed by a main conductor layer having a surface resistance not more than 1.5 times the surface resistance caused by the skin effect. Japanese Laid-Open Patent Publication No. 2004-327745 (Patent Document 5) describes a wiring board in which a high-resistance layer provided on the surface of a wiring pattern for the purpose of preventing oxidation is formed to have a thickness of 1 μm or less, or no high-resistance layer is formed.